How is an SSD made? Understand the technology inside it

We save data to SSDs every day, but have you ever wondered how SSDs are actually made? A device no larger than a few fingers can contain billions of memory cells. To create these cells, engineers fabricate hundreds of layers of microscopic structures onto a thin silicon wafer.

But this raises the real question: how is a memory cell formed within these layers

How is an electrical charge trapped inside, and how does the SSD determine—based on that charge—whether a zero, a one, or even more data is stored there? These tiny cells combine to form NAND flash memory. NAND dies are mounted into packages and integrated with a controller and firmware to create a complete SSD. It is fascinating to understand how a microscopic memory cell can retain our data without any moving parts.

What is a memory cell

Let’s start by understanding the smallest and most crucial component of an SSD: the memory cell. You can think of a memory cell as a microscopic container where the state of an electrical charge can be altered. This charge enables the SSD to store information. However, there is an important distinction here: data isn't simply sitting inside a tiny box within the SSD. Instead, the cell's electrical properties are modified—specifically, its threshold voltage is controlled at various levels. Simply put, threshold voltage is the voltage level at which a transistor begins to conduct electricity. This property is what allows data to be stored.

How is more than one bit stored in a single cell

But why limit a cell to storing just one bit? This is where the story of increasing NAND flash density begins. If only a single bit is stored in a cell, there are two possible states; this is known as SLC, or Single-Level Cell. However, storing two bits in a cell requires four distinct states; this is called MLC, or Multi-Level Cell. Similarly, TLC (Triple-Level Cell) allows for three bits per cell, and QLC (Quad-Level Cell) allows for four. In essence, to extract more data from a single physical cell, engineers must control and detect its electrical charge in a greater number of ways.

From 2D NAND to 3D NAND

However, a new problem arises here. When billions of memory cells are required, fabricating them all on a single flat silicon surface eventually leads to a shortage of space. This is where 3D NAND comes into play. In traditional 2D NAND—also known as Planar NAND—memory cells were primarily arranged side-by-side on the silicon surface. But physical limitations were encountered as engineers tried to make the cells progressively smaller. Engineers then chose a different approach: instead of spreading the cells across a single surface, they began stacking them vertically. This is 3D NAND.

How are 3D NAND layers created

The question now arises: how are these vertical layers constructed? The process begins with a highly pure silicon wafer. The wafer is first cleaned and prepared. Next, very thin layers of material are deposited onto its surface—a process known as deposition. However, simply depositing layers does not create memory; precise patterns must be formed within each layer. To achieve this, a light-sensitive material called photoresist is applied to the wafer. Next, lithography is used to transfer minute patterns. This is followed by etching, a process where material is removed in a controlled manner from areas where it is not required. This process is particularly challenging in 3D NAND because engineers may need to create very deep, narrow vertical holes through a stack comprising hundreds of layers. You can visualize this as creating a vertical tunnel—like a stairwell—from the top to the bottom of a tower with extremely thin walls. However, the real challenge lies beyond merely creating the tunnel; the tunnel must align perfectly from the top layer to the bottom layer. Its dimensions must be precisely controlled, and the structure's uniformity must be maintained throughout its entire depth.

Electrical Structure of the Memory Cell

Memory structures and their electrical control mechanisms are built around this vertical framework. Key components such as word lines, vertical channels, and charge trap structures play a vital role here. Many manufacturers of modern 3D NAND utilize charge trap technology, where electrons are trapped within an insulating layer. It is this trapped charge that alters the transistor's electrical characteristics. We now have a structure containing numerous memory cells arranged vertically. But how can such a vast number of cells be accessed in an organized manner?

Internal Hierarchy of NAND

To understand this, one must look at the internal hierarchy of NAND. Multiple cells combine to form a page, and multiple pages combine to form a block; these, in turn, form higher-level structures such as planes and dies. There is a crucial distinction here: while data in NAND is typically programmed at the page level, the erase operation occurs at the block level. Consequently, if the data in specific pages within a block needs to be modified, the controller must manage the data while taking this inherent limitation of NAND into account. How are NAND dies made from a wafer?

Manufacturing does not end once the NAND structures are formed on the wafer. The entire wafer undergoes testing to identify which memory dies exhibit the correct electrical behavior. Subsequently, the wafer may be thinned to the required thickness before being cut into small, individual pieces. These small silicon pieces are known as NAND dies. One or more dies can then be assembled into a package, and electrical connections are established for them.

What does an SSD controller do

Since NAND cannot directly determine where to store data received from the computer, an SSD controller is required. The controller functions like the central processing unit (CPU) of the SSD; it interprets commands from the computer and manages the actual read and write operations involving the NAND. However, the specific physical location within the NAND does not necessarily correspond directly to the address where the computer intends to write the data.

Flash Translation Layer (FTL)

This is where the Flash Translation Layer (FTL) comes into play. The FTL maps the computer's logical addresses to the physical locations within the NAND. Additionally, the controller employs Error Correction Code (ECC) mechanisms. Errors can occur in NAND over time and with usage; therefore, the controller attempts to detect and correct erroneous bits using supplementary error correction information. Modern SSD controllers may also utilize advanced error correction techniques, such as LDPC (Low-Density Parity-Check).

What is Wear Leveling

The controller's role does not end there. Repeatedly writing data to the same memory cells can cause them to wear out prematurely. To prevent this, the controller uses "wear leveling" to distribute write operations across various NAND locations.

How does Garbage Collection work? When pages containing old data become invalid, the controller can move the valid data elsewhere and then erase and reuse the old blocks. This process is known as Garbage Collection. Similarly, some blocks in the NAND flash may be defective from the time of manufacturing or fail over time; the controller manages these as "Bad Blocks."

How are components mounted on the SSD's PCB

The NAND, controller, and other electronic components are mounted onto a PCB (Printed Circuit Board). In the automated assembly process, solder paste is first applied to the PCB. Machines then place the controller, NAND packages, and other components with high precision. Next, the PCB passes through a reflow oven; the heat melts the solder paste, and upon cooling, the electrical connections for the components are established. Finally, the assembly undergoes optical and electrical inspections.

Why is firmware essential for an SSD?

Following this, firmware is programmed into the controller. The firmware dictates how to:

Initialize the NAND;

Manage data mapping;

Handle errors;

Execute Wear Leveling and Garbage Collection;

And respond to commands from the host computer.

Testing the finished SSD

A finished SSD is not approved based on visual inspection alone; its electrical characteristics, NAND behavior, read/write operations, performance, and reliability are all tested. Only when the hardware, NAND, controller, firmware, and all testing stages prove successful does this small device become a fully functional SSD.

The technology inside an SSD

So, the next time you save a file to an SSD, remember: there is much more behind that small storage device than just a few chips. Inside it, a complex engineering system is at work—comprising microscopic memory cells fabricated on a wafer, hundreds of 3D layers, precise electrical states, NAND architecture, controller algorithms, error correction, and firmware. That is precisely why the technology within an SSD is so vast and intricate, contrasting with its compact external appearance.

Conclusion

Although an SSD may appear to be a small storage device from the outside, it houses various components—such as memory cells, multiple layers of 3D NAND, a controller, memory, error correction mechanisms, and firmware—that work in unison. Memory cells store data via electrical states, while the controller manages data operations, including error correction, wear leveling, and garbage collection. It is through the integration of these components—specifically the NAND storage and the controller—that a complete SSD is formed. This is why, despite its compact size, the technology powering an SSD is remarkably complex and advanced.